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APT7843
Touch Screen Controller
Description
The APT7843 Touch Screen Controller IC provides all the screen drive , A/D converter and control circuits to easily interface to 4 wire resistive touch screen. The IC continually monitors the screen waiting for a touch. When the screen touched , the IC performs A/D converter to determine the location of touch. Also , this device has 2 auxiliary input to A/D converter , allowing for the measurement of other inputs such as battery voltage.
Features * * * * * * *
16 pin SSOP or TSSOP Operates with four wire touch screen 8-bit or 12 bit A/D converter Ratiometric Conversion eliminates screen calibration 2 auxiliary analog inputs 4 wire serial interface Full power down control
Applications * * *
PDAs Handheld computer Touch-screen kiosks
Pin Assignment
+Vcc X+ Y+ XYGND IN3 IN4 1 2 3 4 5 6 7 8 16 15 14 13 12 DCLK CS DIN BUSY DOUT
11 PENIRQ 10 9 +Vcc VREF
Order Information
APT7843
Temp. Range Package Code Package Code N : SSOP Temp. Range I : - 40 to 85 C
O : TSSOP
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.8 - Apr., 2002 1 www.anpec.com.tw
APT7843
Block Diagram
PENIRQ
X+ XScreen Driver
DCLK CS
MUX 12 Bit or 8 Bit A/D Converter Serial Interface
Y+ YIN3 IN4 VREF
DIN
DOUT BUSY
Pin Descriptions
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NAME +Vcc X+ Y+ XYGND IN3 IN4 VREF DESCRIPTION Power Supply,2.2V to 5V. Connect to X+ on touch screen. Connect to Y+ on touch screen. Connect to X- on touch screen. Connect to Y- on touch screen.
Ground Auxiliary Input of A/D converter. Auxiliary input of A/D converter. Voltage Reference Input. +Vcc Power Supply,2.2V to 5V. PENIRQ Pen interrupt. Open anode output (requires 10k to 100k pull-up resistor externally) DOUT Serial Data Output. This output is high impedance when CS is HIGH. BUSY Busy Output. This output is high impedance when CS is HIGH. DIN Serial Data input. CS DCLK Chip Select. (Active Low) Serial Clock.
Copyright ANPEC Electronics Corp. Rev. A.8 - Apr., 2002
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APT7843
Electrical Characteristics
At TA = -40C to 85C , VCC = +2.7V , VREF = +2.5V , fSAMPLE = 125kHz , fCLK = 16 * f SAMPLE = 2MHz , 12-bit mode , and digital inputs = GND or Vcc , unless otherwise noted.
PA R A M E T E R DC ACCURACY R esolu tio n N o m issing co de Integra l N onlin earity O ffset E rror O ffset E rror M atch G ain E rror G ain E rror M atch N oise P ow er S u pply R ejectio n R E F E R A N C E IN P U T V R E F In put Voltage R an ge D C Le akage C urrent V R E F In put Im p eda nce V R E F In put C urrent F S A M P LE = 12 .5 kH z C S = V cc D Y N A M IC P E R F O R E N C E A perture D e lay A perture Jitter C han nel to C han ne l Isolation C O N V E R S IO N R AT E C onversion Tim e Track/H old A cquis ition Tim e T hrough put R ate S W IT C H D R IV E R S O n-R esistance Y+ , X+ Y- , XL O G IC O U T P U T S O utput H ig h Vo lta ge , V O H O utput Low Voltage , V O L PEN IR Q output low voltage , V O L Floating-S tate Leakage C urrent Floating-State Output Capacitance O utput C oding |I O H | -250 A |I O L | 250 A V cc-0.2 0.4 0.2 10 10 S traight ( N atura l ) B in ary V V V A pF 4 4 15 15 3 125 12 DCLK cycles DCLK cycles KSPS V IN = 2.5 V p-p ; F IN = 5 0kH z 30 100 100 ns ps dB C S = G N D or V cc 1.0 1 5 13 2.5 3 40 V cc A G A A A 0.1 30 70 0.1 11 2 6 1 4 1 12 B its B its LS B LS B LS B LS B LS B uV rm s dB C O N D IT IO N S A P T 78 43 M IN TYP MAX U N IT S
Note : (1) LSB means least Significant Bit. With VREF equal to +2.5V , one LSB is 610V
Copyright ANPEC Electronics Corp. Rev. A.8 - Apr., 2002
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APT7843
Electrical Characteristics (Cont.)
PA R A M E T E R L O G IC IN P U T S In p u t H ig h Vo lta g e , V INH In p u t L o w Vo lta g e , V INL Inp ut C urre nt , IIN In p u t C a p a c ita n c e , C IN A N ALO G IN P U T In p u t Vo lta g e R a n g e s D C Le aka ge C u rre nt In p u t C a p a c ita n c e P O W E R R EQ U IR E M EN T S Vcc Ic c N orm a l M o d e (S ta tic ) N orm al M od e (F S A M P L E = 1 2 .5k S P S ) S hutdow n M o d e (S ta tic) Showdown D ig ita l I/P s = 0 V o r V cc V cc = 3.6V V cc = 3.6V 650 540 3 V cc = 3.6V 3.6 A A A W 2.7 3.6 V C O N D IT IO N S APT7843 M IN 2.4 0.8 1 10 0 0.1 30 V REF TYP MAX U N IT S
| I I N H | + 5 A | I I N L | + 5 A
V V A pF Vo lts A pF
Copyright ANPEC Electronics Corp. Rev. A.8 - Apr., 2002
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APT7843
Electrical Characteristics
At TA = -40C to 85C, VCC = +2.4V , VREF don't care, fSAMPLE = 1.25KHz, fCLK = 16 * f SAMPLE = 20KHz, 8-bit differential mode, no support single end mode, and digital inputs = GND or Vcc , unless otherwise noted.
PARAMETER DC ACCURACY Resolution No missing code Integral Nonlinearity Offset Error Offset Error Match Gain Error Gain Error Match Noise Power Supply Rejection DYNAMIC PERFORENCE Aperture Delay Aperture Jitter Channel to Channel Isolation CONVERSION RATE Conversion Time Track/Hold Acquisition Time Throughput Rate SWITCH DRIVERS On-Resistance Y+ , X+ Y- , XLOGIC OUTPUTS Output High Voltage , VOH Output Low Voltage , VOL PENIRQ output low voltage , VOL Floating-State Leakage Current Floating-State Output Capacitance Output Coding
CONDITIONS
APT7843 MIN TYP 8 7 2 6 0.1 0.1 30 70 30 100 1 4 1 MAX
UNITS
Bits Bits LSB LSB LSB LSB LSB uV rms dB ns ps dB 12 DCLK cycles DCLK cycles 1.25 KSPS
VIN = 2.5Vp-p ; FIN = 50kHz
100
3
4 4 |IOH| -250A |IOL| 250A Vcc-0.2 0.4 0.2 10 10 Straight ( Natural ) Binary
V V V A pF
Copyright ANPEC Electronics Corp. Rev. A.8 - Apr., 2002
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APT7843
Electrical Characteristics (Cont.)
PA R A M E T E R L O G IC IN P U T S In p u t H ig h Vo lta g e , V IN H In p u t L o w Vo lta g e , V INL In p u t C urr e n t , IIN In p u t C a p a c it a n c e , C IN A NALOG IN PUT In p u t Vo lt a g e R a n g e s D C Leakage C urrent In p u t C a p ac ita n c e P O W E R R E Q U IR E M E N T S Vcc Ic c N orm a l M o d e (S ta tic ) N orm a l M o de (F S A M P L E = 1 2.5k S P S ) S h u td o w n M o d e (S ta tic) Showdown D ig ita l I/P s =0 V o r V cc V cc = 2.4V V cc = 2.4V V cc = 2.4V 280 650 540 3 3.6 A A A W 2.2 2.4 3.6 V 0 0 .1 30 V REF Vo lts A pF | I I N H | + 5 A | I I N L | + 5 A 2.2 VDD+0.2 0.6 1 10 V V A pF C O N D IT IO N S APT7843 M IN TYP MAX U N IT S
Copyright ANPEC Electronics Corp. Rev. A.8 - Apr., 2002
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APT7843
Chip Overview
The APT7843 is a successive approximation analogto-digital (A/D) converter based around a capacitive redistribution DAC. Figure 1 show basic operation of the APT7843. The APT7843 communicates via a 4-wire serial interface. The device also requires an external reference voltage Vref. The value of the reference voltage directly sets the input range of the converter. The APT7843 primary function is to control resistive touchscreens. When a touch is detected , pen interrupt pin will go low to wake up extenal microprocess. The microprocessor writes register to initiate conversion. This A/D converter may also be used to measure voltage presented on the IN3 , IN4 pins.
Analog Input
The analog input to the converter is provided via a four-channel multiplexer. Figure 2 shows a simplified diagram of the APT7843 with the difference input of the A/D converter , and the converter's reference. Table I and Table II also show the relationship between the A2 , A1 , A0 , SER/ DFR and the configuration of the APT7843. See the section of single-ended reference mode and differential reference mode for more details.
+2 .2 V to +5 V
1u F to 10 uF (O ptio nal)
0.1u F
1
A P T 784 3 +V c c X+ Y+ XYGND IN 3 IN 4 DCLK CS D IN BUSY DOUT P E N IR Q +V c c V RE F
16 15 14 13 12 11 10 9
2 3 4 5 6 7
To T o uch S c ree n
C on nec t to M icropros sor
A u xiliary Inpu t
8
10 0k oh m (op tion al) 0.1u F
FIGURE 1. Basic Operation of the APT7843
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APT7843
PENIRQ +Vcc VREF
A2-A0 (Shown 001B)
SER/DFR (Shown HIGH)
X+ X-
Y+ Y-
+IN -IN
+REF CONVERTER -REF
IN3 IN4 GND
FIGURE 2. Simplified Diagram of Analog Input
A2 0 1 0 1
A1 0 0 1 1
A0 1 1 0 0
X+ +IN
Y+ +IN
IN3
IN4
+IN +IN
-IN GND GND GND GND
X SWITCHES Y SWITCHES OFF ON ON OFF OFF OFF OFF OFF
+REF +VREF +VREF +VREF +VREF
-REF GND GND GND GND
TABLE I. Input C onfiguration, Single-Ended Reference Mode (SER/ DFR HIGH).
A2 0 1 0 1 A1 0 0 1 1 A0 1 1 0 0 X+ +IN Y+ +IN +IN +IN IN3 IN4 -IN -Y -X GND GND X SWITCHES Y SWITCHES OFF ON ON OFF OFF OFF OFF OFF +REF +Y +X +VREF +VREF -REF -Y -X GND GND
TABLE II. Input Configuration, Differential Reference Mode (SER/ DFR LOW).
Copyright ANPEC Electronics Corp. Rev. A.8 - Apr., 2002
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APT7843
Single-Ended reference mode
Figure 3 shows the diagram of single-ended reference mode. This application shows the measurement of current Y poisition is made by connecting the X+ input to the A/D converter, turning on the Y+ and Y- drivers, and digitizing the voltage on X+ . For this measurement, the resistance in the X+ lead does not affect the conversion. However, since the resistance between Y+ and Y- is fairly low, the on-resistance of the Y drivers does make a small difference. Under the situation outlined so far, it would not be possible to achieve a zero volt input or a full-scale input regardless of where the pointing device is on the touch screen because some voltage is lost across the internal switches. This situation can be remedied if use differential reference mode
+Vcc
Y+ Y+ X+
+IN +REF
Converter
-IN -REF
Y-
YY Switch ON
GND
Figure 4. Differential Reference Mode (SER/DFR LOW, A2=Low,A1=Low,A0=High)
+Vcc
Serial Interface
Data is written to,and read from , the APT7843 via the serial port. The serial port has 4 pins - serial clock (DCLK),chip select ( CS ) ,data in (DIN) and data out (DOUT). The DCLK acts on the rising edge. The CS acts as a reset for the serial port with CS goes low initating a conversion cycle. The cycle consists of 2 parts - a write followed by a read. Figure 5 shows the typical timing of the APT7843's serial interface. A total of 24 clock cycles will complete one conversion. Also shown in Figure 5 is the placement and order of the control bits within the control byte. Tables III and IV give detailed information about these bits. The first bit, the S bit, must always be HIGH and indicates the start of the control byte. The APT7843 will ignore inputs on the DIN pin until the start bit S detected. The next three bits (A2 - A0) select the active input channel or channels of the input multiplexer (see Tables I and II and Figure 2). The MODE bit determines the number of bits for each conversion, either 12 bits (LOW) or 8 bits (HIGH). The SER/DFR bit controls the reference mode: either single-ended (HIGH) or differential (LOW). (The differential mode is also referred to as the ratiometric conversion mode.) The last two bits (PD1 - PD0) select the power- down mode as shown in Table V. If both inputs are HIGH, the device is always powered up. If both inputs are LOW, the device enters a power-down mode between conversions.
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Y+ VREF X+
+IN +REF
Converter
-IN -REF
Y-
GND
Y Switch ON
GND
FIGURE 3.Single-Ended Reference Mode (SER/DFR High, A2=Low,A1=Low,A0=High)
Differential reference mode
As shown in Figure 4,by setting the SER/ DFR bit LOW, the +REF and -REF inputs are connected directly to Y+ and Y-. This makes the analog-to- digital conversion ratiometric. The result of the conversion is always a percentage of the external resistance, reardless of how it changes in relation to the on-resistance of the internal switches. Note that there is an important consideration regarding power dissipation when using the ratiometric mode of operation,the external device should powered throughout the acquisition and conversion periods.
Copyright ANPEC Electronics Corp. Rev. A.8 - Apr., 2002
APT7843
Bit 7 (MSB) S Bit 6 A2 Bit 5 A1 Bit 4 A0 Bit 3 Bit 2 Bit 1 PD1 Bit 0 (LSB) PD0 PD1 PD0 0 0 PENIRQ DESCRIPTION Enabled Power-down between conversions. When each conversion is finished, the converter enters a low power mode. Enabled Reserved for future use Enabled Reserved for future use. Disabled No power-down between conversions, device is always powered.
MODE SER/DFR
TABLE III. Order of the Control Bits in the Control Byte.
BIT 7 NAME S DESCRIPTION
0 1 1
1 0 1
6-4
2
1-0
Start Bit. Control byte starts with first HIGH bit on DIN. A new control byte can start every 15th clock cycle in 12-bit conversion mode or every 11th clock cycle in 8-bit conversion mode. A2-A0 Channel Select Bits. Along with the SER/DFR bit, these bits control the setting of the multiplexer input, switches, and reference inputs, as detailed in Tables I and II. MODE 12-Bit/8-Bit Conversion Select Bit. This bit controls the number of bits for the following conversion: 12bits(LOW) or 8-bits(HIGH). SER/DFR Single-Ended/Differential Reference Select Bit. Along with bits A2-A0, this bit controls the setting of the multiplexer input, switches, and reference inputs, as detailed in Tables I and II. PD1-PD0 Power-Down Mode Select Bits. See Table V for details.
TABLE V. Power-Down Selection.
TABLE IV. Descriptions of the Control Bits within the Control Byte.
CS
DCLK
1 tACQ S
A2 A1 ldle A0
MODE SER/ DFR
8
1
8
1
8
DIN
PD1 PD0
(START) Acquire Conversion ldle
BUSY
DOUT
11 10 9
(MSB)
87
6
5
4
3
2
1
0
(LSB)
FIGURE 5. Conversion Timing, 24-Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required with Dedicated Serial Port.
Copyright ANPEC Electronics Corp. Rev. A.8 - Apr., 2002
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APT7843
CS
DCLK 1 S
CONTROL BITS
8
1
8
1 S
CONTROL BITS
8
1
DIN
BUSY
DOUT
11 10 9 8 7 6 5
43210
11 10 9
FIGURE 6. Conversion Timing, 16-Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required with Dedicated Serial Port.
16-Clocks or 15-Clocks per Conversion
The APT7843 will alow a conversion every 16 clock cycles, as shown in Figure 6. This figure shows possible serial communication occurring with other serial peripherals between each byte transfer between the processor and the converter. Figure 7 provides the fastest way to clock the APT7843. This method will not work with the serial interface of most microcontrollers and digital signal processors as they are generally not capable of providing 15 clock cycles per serial transfer. However, this method could be used with field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs). (Note that this effectively increases the maximum conversion rate of the converter).
AC Timing
Figure 8 and Table VI provide detailed timing of the APT7843. Table VII provide detailed timing of low power VCC=2.4V.
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APT7843
SYMBOL DESCRIPTION MIN TYP MAX UNIT SYMBOL DESCRIPTION MIN TYP MAX UNIT
tACQ tDS tDH tDO tDV tTR tCSS tCSH tCH tCL tBD tBDV tBTR
Acquisition Time DIN Valid Prior to DCLK Rising DIN Hold After DCLK HIGH DCLK Falling to DOUT Vaild CS Falling to DOUT Enabled CS Rising to DOUT Disabled CS Falling to DCLK Rising CS Rising to DCLK lgnored DCLK HIGH DCLK LOW DCLK Falling to BUSY Rising CS Falling to BUSY Enabled CS Rising to BUSY Disable
1.5 100 10 200 200 200 100 0 200 200 200 200 200
s ns ns ns ns ns ns ns ns ns ns ns ns
tACQ tDS tDH tDO tDV tTR tCSS tCSH tCH tCL tBD tBDV tBTR
Acquisition Time DIN Valid Prior to DCLK Rising DIN Hold After DCLK HIGH DCLK Falling to DOUT Vaild CS Falling to DOUT Enabled CS Rising to DOUT Disabled CS Falling to DCLK Rising CS Rising to DCLK lgnored DCLK HIGH DCLK LOW DCLK Falling to BUSY Rising CS Falling to BUSY Enabled CS Rising to BUSY Disable
20 400 20 400 400 400 200 0 2.5 2.5 400 400 400
s ns ns ns ns ns ns ns s s ns ns ns
TABLE VI. Timing Specifications (+Vcc=+2.7V and Above, TA=-40C to +85C, CLOAD=50pF).
TABLE VI. Timing Specifications (+Vcc=+2.4V and Above, TA=-40C to +85C, CLOAD=50pF).
CS
DCLK 1 DIN S
A2 A1 A0
MODE SGL/ DIF
15 1
PD1 PD0
15 1
A2 A1 A0
MODE SGL/ DIF
S
PD1 PD0
S
A2 A1 A0
BUSY
DOUT
11 10 9 8 7 6 5 4 3 2 1 0
11 10 9 8 7 6 5 4 3 2
FIGURE 7. Maximum Conversion Rate, 15-Clocks per Conversion.
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APT7843
CS tCSS DCLK tDS DIN tBDV BUSY tDH
PD0
tCH
tCL
tBD
tBD
tBD
tCSH
tBTR
DOUT
tDV 11 10
tTR
FIGURE 8. Detailed Timing Diagram.
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APT7843
Packaging Information
SSOP
D N
H
E
GAUGE PLANE
123 A e B A1 L
1
Millimeters Dim A A1 B D E e H L N 1 Min. 1.350 0.10 0.20 3.75 5.75 0.4 0 Max. 1.75 0.25 0.30 4.05 6.25 1.27 8
Variations- D Variations SSOP-16 Min. 4.75 Max. 5.05 Dim A A1 B D E e H L N 1
Inches Min. 0.053 0.004 0.008 0.147 0.226 0.016 0 0.069 0.010 0.012 0.160 0.246 0.050 8
Variations- D Min. 0.187 Max. 0.199 SSOP-16
Max. Variations
See variations 0.625 TYP.
See variations 0.025 TYP.
See variations
See variations
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APT7843
Packaging Information
TSSOP
e N
2x E/2 E1 E ( 2)
GAUGE PLANE
123
e/2
D
A2 A
0.25
L
1
b
A1
( 3)
Dim A A1 A2 b D e E E1 L 1 2 3
Millimeters Max. 1.2 0.00 0.15 0.80 1.05 0.19 0.30 5.1 (N=16PIN) 4.9 (N=16PIN) 6.6 (N=20PIN) 6.4 (N=20PIN) 7.9 (N=24PIN) 7.7 (N=24PIN) 9.8 (N=28PIN) 9.6 (N=28PIN) 0.65 BSC 6.40 BSC 4.30 4.50 0.45 0.75 0 8 12 REF 12 REF Min. Min.
Inches Max. 0.047 0.000 0.006 0.031 0.041 0.007 0.011 0.201 (N=16PIN) 0.193 (N=16PIN) 0.260 (N=20PIN) 0.252 (N=20PIN) 0.311 (N=24PIN) 0.303 (N=24PIN) 0.386 (N=28PIN) 0.378 (N=28PIN) 0.026 BSC 0.252 BSC 0.169 0.177 0.018 0.030 0 8 12 REF 12 REF
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APT7843
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb) Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
(IR/Convection or VPR Reflow)
temperature
Peak temperature
183C Pre-heat temperature
Time
Classification Reflow Profiles
Convection or IR/ Convection Average ramp-up rate(183C to Peak) 3C/second max. 120 seconds max Preheat temperature 125 25C) 60 - 150 seconds Temperature maintained above 183C Time within 5C of actual peak temperature 10 -20 seconds Peak temperature range 220 +5/-0C or 235 +5/-0C Ramp-down rate 6 C /second max. 6 minutes max. Time 25C to peak temperature VPR 10 C /second max.
60 seconds 215-219C or 235 +5/-0C 10 C /second max.
Package Reflow Conditions
pkg. thickness 2.5mm and all bgas Convection 220 +5/-0 C VPR 215-219 C IR/Convection 220 +5/-0 C pkg. thickness < 2.5mm and pkg. volume 350 mm pkg. thickness < 2.5mm and pkg. volume < 350mm Convection 235 +5/-0 C VPR 235 +5/-0 C IR/Convection 235 +5/-0 C
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APT7843
Reliability test program
Test item SOLDERABILITY HOLT PCT TST Method MIL-STD-883D-2003 MIL-STD 883D-1005.7 JESD-22-B, A102 MIL-STD 883D-1011.9 Description 245C,5 SEC 1000 Hrs Bias @ 125C 168 Hrs, 100% RH, 121C -65C ~ 150C, 200 Cycles
Carrier Tape & Reel Dimensions
t E Po P P1 D
W
F
Bo
Ao
D1 T2
Ko
J C A B
T1
Application
A 6.95
B 5.4 T2 2.2
D0
D1
E 1.750.1 C1 130.3
F 5.50.05 C2 210.8
P0 4.00.1 T1 13.50.5
P1 8.00.1 T2 2.00.2
P2 2.00.05 C 801
1.550.05 1.550.1 W 12.00.3 W1 9.5
SSOP-14/16
T 0.30.05
(mm)
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APT7843
Customer Service
Anpec Electronics Corp. Head Office : 5F, No. 2 Li-Hsin Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
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